Description: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。
基于达到达到达到的信号发生器的源程序-Digital baseband signal transmission is a digital communications system, an important component. In digital communication, there are some occasions, may from time through the carrier modulation and demodulation process, the base-band signal for direct transmission. AMI code signal using alternating inversion, there may be four to zero with the phenomenon, which is not conducive to the receiving end of the timing signal extraction. The HDB3 code because of its non-DC components, low-frequency components, and even a small number of 0 up to more than three characteristics, while the timing signal recovery is very favorable, and has become CCITT Association recommended one of baseband transmission pattern. In this paper the use of VHDL language for data transmission system in the HDB3 encoder has been designed. Based on the signal generator to achieve to reach to reach the source Platform: |
Size: 3072 |
Author:成风 |
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Description: 信号发生器是一种常用的仪器，能够实现各种波形，不同频率的输出，电子测试系统的重要部件。本研究
的数字信号发生器足基于直接数字合成即DDS技术设计的，采用VHDL与C语言相结合的方法，通过查找存储
于ROM查找表中的各种标准波形数据，产牛频率Hf调并且高精度的正弦波、方波、锯齿波等常用信号，并且町
以通过修改表中的数据，实现任意信号发生器-Signal generator is a commonly used instrument to achieve a variety of waveforms of different frequency output, a key component of electronic test systems. In this study, full digital signal generator that is based on DDS technology of direct digital synthesis design, VHDL and C language using the method of combining, by looking up stored in ROM look-up table in a variety of standard waveform data, the cattle and the high frequency tone Hf accuracy of the sine wave, square wave, sawtooth and other signals used, and town to modify table data, an arbitrary signal generator Platform: |
Size: 268288 |
Author:姚木 |
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Description: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible Platform: |
Size: 60416 |
Author:badfox |
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Description: FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode converter) 6 Platform: |
Size: 2048 |
Author:hucy |
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Description: VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the state controller, the program counter and address multiplexer Platform: |
Size: 6144 |
Author:林琳 |
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Description: vhdl实现FSK调制，本次毕业设计的数据速率 1.2kb/s，要求产生一个1.2kHz的正弦信号，对正弦信号每周期取100个采样点，因此要求产生3个时钟信号：1.2kHz（数据速率）、120kHz（产生1.2kHz正弦信号的输入时钟）、240kHz（产生2.4kHz正弦信号的输入时钟）。基准时钟已由一个外部时钟120MHz提供，要得到前面三种时钟，就需要首先设计一个模50的分频器产生240kHz信号，再设计一个二分频器，生产一个120kHz的信号，然后再前面的基础上再设计一个模100的分频器，用来产生1.2kHz的随机信号产生速率。-vhdl achieve FSK modulation, the graduate design data rate of 1.2kb/s to produce a sinusoidal signal of 1.2kHz, take the 100 sampling points per cycle of the sinusoidal signal, thus requiring to produce the three clock signals: 1.2 kHz (data rate , 120kHz, a 1.2kHz sine input clock signal), 240kHz (a 2.4kHz sine signal input clock). 120MHz reference clock has been an external clock to get the first three clock, you need to first design a mold 50 of the divider to produce a 240kHz signal, re-design of a two frequency divider to produce a 120kHz signal, and then the front of the base on the re-design of a mold 100 of the divider used to generate the 1.2kHz random signal generator rate. Platform: |
Size: 1024 |
Author:杨 |
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